(1) Field of the Invention
The present invention relates to the fabrication of integrated circuits, and more particularly to a method for forming improved shallow trenches which minimizes the wrap-around corner effect that enhances the gate control of the top trench conduction path along the isolation edge between the source and drain, and causes sub-threshold "hump" of I.sub.d -V.sub.G curves at substrate back bias.
(2) Description of the Prior Art
Various field oxide (FOX) isolations are used to electrically isolate the discrete semiconductor devices, such as field effect transistors (FETs), formed in and on semiconductor substrates. This FOX is formed on single crystal silicon (Si) for Ultra Large Scale Integration (ULSI) circuit applications. One common method of forming the field oxides in the semiconductor industry is by the local oxidation of silicon (LOCOS) method. LOCOS uses a patterned silicon nitride (Si.sub.3 N.sub.4) as an oxidation barrier mask and the silicon substrate is selectively oxidized to form the semi-planar isolation. However, this method requires long oxidation times (excessive thermal budgets) and the lateral oxidation under the barrier mask limits the minimum spacing between adjacent active device areas and therefore prevents further increase in device packing density.
In more advanced isolation schemes, to minimize the FOX feature size for ULSI, it is common practice to etch shallow trenches in the silicon substrate which are then filled with a chemical vapor deposited (CVD) silicon oxide (SiO.sub.2). The CVD oxide is then either etched back or chemical mechanical polished (CMP) back to form the FOX, which is commonly referred to as Shallow Trench Isolation (STI).
However, there are several problems associated with the conventional or prior art shallow trench isolation methods. These problems are best understood by referring to the prior art shown in FIGS. 1 through 6 in which a sequence of schematic cross-sectional views is shown of the process steps. As shown in FIG. 1, the prior art method starts by forming a stress-release pad oxide (SiO.sub.2) layer 12 on the silicon substrate 10, and then depositing a chemical vapor deposited (CVD) silicon nitride (Si.sub.3 N.sub.4) layer 14. Conventional photolithographic techniques are then used to pattern the silicon nitride layer 14, the pad oxide 12 and to etch trenches 1 in the substrate 10. After removing the photoresist mask (not shown) a liner oxide layer 16 is grown on the exposed silicon surface in the trenches 1 by thermal oxidation, as shown in FIG. 2. A Low Pressure CVD (LPCVD), a Sub-Atmosphere CVD (SACVD), or High-Density Plasma CVD (HDP-CVD) silicon oxide 18 is then deposited to fill the trenches 1, as shown in FIG. 3. Now as shown in FIG. 4, the CVD silicon oxide is etched back or CMP back to the silicon nitride layer 14. Typically the etch back or polish back of the CVD oxide layer 18 to the silicon nitride hard mask 14 is not very selective and it is difficult to control the etch or polish back within the required processing tolerances. Next, as shown in FIG. 5, the silicon nitride layer 14 is selectively removed using a hot phosphoric acid etch, and the pad oxide layer 12 is removed using dilute hydrofluoric (HF) acid to expose the active device areas. Unfortunately this results in a recess 2 in the field oxide at the edge of the device areas 3.
Now as shown in FIG. 6, when the FET gate oxide 20 is grown on the device areas 3, a polysilicon layer 22 is deposited and patterned to form the FET gate electrodes 22. The wrap-around corner effect in the recess 2 at the edge of the device area results in a crowded gate electric field (E) that causes an enhanced corner conduction path along the isolation edge between the source and drain, and results in a subthreshold "hump" of I.sub.d -V.sub.G curves at substrate back bias (increase of I.sub.d at low V.sub.G). Furthermore, the non-uniformity from the CMP across the substrate results in large variations in the gate threshold voltage (V.sub.th) due to the variation in electric field (E) FET. The wrap-around corner effect can also increase the sub-threshold current which is also very undesirable for low voltage applications.
Several related references include "Characteristics of CMOS Device Isolation for the ULSI Age," by A. Bryant et al., IEDM Tech. Dig., pages 671-674, 1994, in which the enhanced corner edge conduction is observed at low gate voltages with high substrate doping and back bias. "A Study of Integration Issues in Shallow Trench Isolation for Deep Submicron CMOS Technologies," by A. Chatterjee et al., SPIE, Vol. 2875, pages 39-47, 1996, in which the various process choices for making a shallow trench isolation structure are described, and particularly in relation to forming the liner oxidation for the shallow trench.
Another approach is described in U.S. Pat. No. 5,567,553 by L. L. Hsu et al. in which the gate electrode is patterned to have a wider channel length over the shallow trench edge relative to the channel length between the trench edges. Still another approach is described in U.S. Pat. No. 5,580,815 by T. C. Hsu et al. in which an annealed amorphous silicon layer is used to minimize the encroachment of the field oxide (bird's beak) into the device area. Another approach is described by Mandelman in U.S. Pat. No. 5,521,422 in which gate wrap-around and corner parasitic leakage are prevented by using a sidewall on the shallow trench isolation.
Although there are a number of methods for forming shallow trenches, there is still a strong need to provide an improved method for forming shallow trenches which circumvent the wrap-around corner effect to improve the device reliability.